CODAS (CO-Design of Accelerated Systems)
My supervision area is on system architectures from designing computer architectures and systems to efficiently leverage them.
Current Members
PhD Students
- Giuseppe Sorrentino (2023-), heterogeneous and adaptive accelerators for Federated Biomedical Image Registration (co-advised with Marco Domenico Santambrogio)
- Omar Regantini (2024-), power-efficient guidance in the deep-space (primary advisor Alessandro Morselli)
- Claudio Di Salvo (2026-), adaptable accelerators for space and biomedical computing systems (co-advised with Marco Domenico Santambrogio)
- Marco Laurenzi (2026-), CXL accelerators at scale (co-advised with Marco Domenico Santambrogio)
Graduate Students
Master Thesis
- Roberto A. Bertolini (2024-): Page Walking Security (co-advised with Lorenzo Binosi)
- Sera Conti (2026-): Quantum Systems Reliability, joint project with Salahuddin Nur (TU Delft) and University of Sao Paulo
- Juan Martin Sanchez Bardellini (2026-): efficient ML models and systems on FPGA-based NPUs (co-advised with Claudio Di Salvo)
Research Projects
- Andrea Oggioni (2025-): accelerating nengo neuromorphic computations on NPUs (co-advised with Giuseppe Sorrentino)
- Gianmaria Napolitano (2026-): HPC RISCV on FPGAs (co-advised with Claudio Di Salvo)
- Federica Valentino (2023-2026): Performance Monitoring of Domain-Specific Archtiectures, Quantum Error Correction on FPGAs
- Chengen Wu (2026-): Exploiting Versal HBM Systems (co-advised with Claudio Di Salvo)
- Alessandro Palliccia (2026-) Efficient Spiking Models on Digital Systems (co-advised with Giuseppe Sorrentino)
Past Members
Graduate Students
Master Thesis
- Valentino Guerrini (2023-2026): Fully Homomorphic Encryption Accelerator on Embedded and High-end FPGAs (co-adivsed with Giuseppe Sorrentino)
- Pier Guido Seno (2026): compilation and execution of regex on heterogeneous systems (co-advised with Giuseppe Sorrentino)
- Giacomo Brunetta (2024-2026): vectorized logarithm and spatial accelerators (co-advised with Giuseppe Sorrentino)
- Marco Laurenzi (2025-2026): direct memory access for NPU-GPU accelerators (co-advised with Giuseppe Sorrentino)
- Paolo Salvatore Galfano (2023-2026): Accelerated MX SoC (work @ Pulp group, ETH, Luca Benini), Heterogeneous System Acceleration through AIE-FPGAs for Image Registration (co-advised with Eleonora D’Arnese)
- Alessandro A. Marina (2024-2026): Spatial Accelerator for Regular Expression matching
- Simone Mannarino (2023-2025): enabling eBPF offloading in OpenNIC (co-advised with Gianni Antichi)
- Claudio Di Salvo (2024-2025): On satellite Image Registration on Embedded FPGAs (co-adivsed with Giuseppe Sorrentino)
- Paolo Ritirato (2024-2025): On satellite telemetry Anomaly Detection with Sipiking Neural Networks on FPGAs (co-advised with Giuseppe Sorrentino)
- Tristan Van Den Weghe (2024): An Emulation-based Approach for Fast Design Space Exploration of a Domain-Specific Architecture for Regex Matching
- Luisa Cicolini (2023-2024): One Automaton To Rule Them All: Beyond Multiple Regular Expressions Execution (co-advised with Filippo Carloni)
- Giuseppe Sorrentino (2022-2023), HEPHAESTUS: an FPGA-based Framework for 3D Image Registration (co-advised with Eleonora D’Arnese)
Research Projects
- Giulio Mantovi and Davide Paltrinieri (2025-2026): machine learning applications on ryzen AI SoC (co-advised with Giuseppe Sorrentino)
- Juan Martin Sanchez Bardellini and Felipe Esteban Puente Cárdenas (2024-2026) machine learning medical image registration at edge on FPGAs (co-advised with Giuseppe Sorrentino)
- Rey Paraula and Roberto Petenzi (2025-2026) high performance computer architectures and their security (co-advised with Alessandro Bertani)
- Amirreza Kiani (2025-2026): AIE-ML image transformation and interpolation (co-advised with Giuseppe Sorrentino)
- Andrea Somaini (2024-2025): Hardware/Software co-design for regex DSA
Undergraduate Students
- Andrea Oggioni (2025): accelerating nengo neuromorphic computations on NPUs (co-advised with Giuseppe Sorrentino)
- Roberto A. Bertolini (2023-2024): Symmetric Cryptography Accelerator on low-end FPGAs
Visiting
- Elouan Lucas, ESEO (summer 2025): efficient AI on Zynqs MPSoCs